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The HPE Intel Xeon E5-2695 v4 processor is a powerful solution specifically designed for use in server environments. With an advanced 14nm lithography and a 64-bit architecture, this processor offers high efficiency and performance. It features 18 cores and supports up to 36 threads, ensuring excellent multitasking capabilities. The maximum clock frequency of 3.3 GHz in Turbo mode allows for dynamic performance adjustments to meet the demands of demanding applications. The processor supports DDR4 SDRAM and can manage up to 1.54 TB of RAM, making it ideal for memory-intensive tasks. With a maximum Thermal Design Power (TDP) of 120 watts, it is also energy-efficient and suitable for use in modern data centers.

- Supports up to 1.54 TB of DDR4 RAM for high memory capacity
- 36 threads and 18 cores for efficient multitasking
- Maximum Turbo clock frequency of 3.3 GHz for dynamic performance
- Quad-channel memory architecture for improved bandwidth
- 45 MB L3 cache to optimize data processing.

Actual product image HPE BL460c Gen9 E5-2695v4 Kit (LGA 2011-v3, 2.10 GHz, 18 -Core)

Key specifications

Processor family

Number of processor cores

A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores (normally a CPU) into a single package composed of a single integrated circuit (IC), called a die, or more dies packaged together. A dual-core processor contains two cores, and a quad-core processor contains four cores.

Number of threads

Max. TDP

The thermal design power (TDP), sometimes called thermal design point, refers to the maximum amount of power the cooling system in a computer is required to dissipate. For example, a laptop's CPU cooling system may be designed for a 20 watt TDP, which means that it can dissipate up to 20 watts of heat without exceeding the maximum junction temperature for the computer chip. It can do this using an active cooling method such as a fan or any of the three passive cooling methods, convection, thermal radiation or conduction. Typically, a combination of methods is used. The TDP is typically not the most power the chip could ever draw, such as by a power virus, but rather the maximum power that it would draw when running "real applications". This ensures the computer will be able to handle essentially all applications without exceeding its thermal envelope, or requiring a cooling system for the maximum theoretical power (which would cost more but in favor of extra headroom for processing power).

L3 Cache

Another issue is the fundamental tradeoff between cache latency and hit rate. Larger caches have better hit rates but longer latency. To address this tradeoff, many computers use multiple levels of cache, with small fast caches backed up by larger slower caches.

Multi-level caches generally operate by checking the smallest Level 1 (L1) cache first; if it hits, the processor proceeds at high speed. If the smaller cache misses, the next larger cache (L2) is checked, and so on, before external memory is checked.

As the latency difference between main memory and the fastest cache has become larger, some processors have begun to utilize as many as three levels of on-chip cache.

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