Eine leistungsstarke Universal-Gate-Implementierung mit geringem Stromverbrauch

A new technique for power reduction called Voltage Scaling Stacked Transistor (VS-STACK) has been introduced. The proposed technique was compared with some existing power reduction methods. The results show a colossal reduction in power consumption for the 2-input NOR gate, with power consumption reduced by 20% to 90%. Additionally, there is a significant improvement in the power-delay product. Therefore, this technique can be used for high-speed circuits. The circuit operates in the sub-threshold region, making it suitable for applications that require extremely low power consumption.